CDC536 driver equivalent, 3.3-v phase-lock-loop clock driver.
* Low-Output Skew for Clock-Distribution and Clock-Generation Applications
* Operates at 3.3-V VCC
* Distributes One Clock Input to Six Outputs
* One Sele.
* Operates at 3.3-V VCC
* Distributes One Clock Input to Six Outputs
* One Select Input Configures Three Out.
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with.
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